The present invention relates to a method of producing a high-resistivity silicon wafer. More particularly, the present invention relates to a method of producing a high-resistivity silicon wafer which utilizes heat treatment during device fabrication to obtain a wafer with a predetermined resistivity.
High resistivity silicon wafers have conventionally been used for power devices such as high-voltage power devices and thyristors. More recently, C-MOS devices, Schottky barrier diodes, and other semiconductor devices for use in mobile communications have been developed which require the use of high-resistivity silicon wafers. The high-resistivity wafers tend to decrease the effects of parasitic capacitance among the devices of the wafer, allowing the devices to be more closely packed upon the surface of the wafer while, at the same time, reducing signal transmission loss among the devices.
The resistivity of the silicon wafer influences and affects the operation of the devices installed upon the surface of the wafer. Devices and circuits are engineered to operate on substrates having particular resistivity values. If the resistivity value of the wafer is different from that which the circuit is designed for, or if the resistivity value of the wafer varies during operation of the circuit, the circuit is likely to fail. Thus, by the time the circuit becomes operational, the resistivity must be set at the proper value and must remain constant during the life of the circuit.
High-resistivity wafers are generally defined as those silicon wafers with resistivity of 100 xcexa9xc2x7cm or greater, and typically have resistivity of 1000 xcexa9xc2x7cm or greater. The initial resistivity of a wafer is established during crystal growth by the precise addition of dopants to the molten polysilicon from which the silicon crystal is formed. By doping, the resistivity of the crystals can be controlled within close tolerances. However, the initial resistivity may be altered, desirably or undesirably, during subsequent processing of the wafer such that the final resistivity of the wafer may be very different from the resistivity directly after crystal growth. For instance, heat treatment during installation of devices within the surface portion of the wafer often causes undesirable variations in the resistivity of the wafer.
In order to form more devices from a single wafer and therefore reduce the cost per device, larger wafers are generally preferred. As such, while high resistivity silicon wafers may be fabricated by a float zone technique, the limitations on one size of the resulting wafers make the Czochralski (CZ) crystal growing method the desired fabrication technique. The CZ method allows wafers having diameters of 200 mm, 300 mm, 400 mm, or larger to be produced. In addition to the large wafer diameter, the CZ method also provides wafers with excellent planar resistivity distribution. Good planar resistivity distribution means that the wafer has only minimal variations in resistivity along the plane which was perpendicular to the growth direction of the crystal during crystal growth.
Unfortunately, there are some problems related to the presence of oxygen during the growth of high-resistivity silicon wafers in a CZ apparatus. During crystal growth within a CZ apparatus, oxygen from the quartz crucible tends to be introduced into the silicon crystal and is maintained in the interstitial spaces of the silicon crystal lattice. The interstitial oxygen atoms are normally electrically neutral, but the oxygen atoms tend to agglomerate as oxygen-containing thermal donors (OTDs), which become electron donors when subjected to heat in the range of 350xc2x0 C. to 500xc2x0 C. Because of electron donation from the OTDs, the resistivity of the wafer may be unfavorably decreased by relatively mild heat treatments subsequent to wafer fabrication. The decreace in resistivity due to the oxygen is especially problematic since temperatures in the range of 350xc2x0 C. to 500xc2x0 C. are commonly encountered during device installation process steps which occur subsequent to wafer fabrication, such as during device fabrication.
The seemingly obvious solution of eliminating oxygen from the silicon lattice is not a complete solution to the problem of resistivity variation within a silicon wafer. The presence of oxygen within the silicon crystal causes bulk defects to form within the crystal. Though large numbers of bulk defects are not desired, small numbers of bulk defects contribute to a gettering effect within the crystal. By gettering, the oxygen derived defects within the crystal act to trap metallic and mobile ionic contamination and to prevent the contamination from traveling to the surface of the wafer. The gettering effect is very important in protecting the devices on the surface of the wafer from interference from the contaminants. Thus, some oxygen is desirable, although too much oxygen is disadvantageous in that it will likely decrease the resistivity of the silicon wafer.
As described in European Patent Office publication EP 1087041 A1, incorporated herein by reference, there is known a method of producing a high-resistivity wafer having a high gettering effect while preventing the reduction of resistivity due to electrons being donated from OTDs upon subsequent heating cycles of the wafer. The method includes first producing a single crystal ingot having a resistivity of 100 xcexa9xc2x7cm or greater and an initial interstitial oxygen concentration of 10 to 25 parts per million atomic (ppma) by a CZ method. Interstitial oxygen is then precipitated with a gettering heat treatment step until the residual interstitial oxygen concentration in the wafer becomes about 8 ppma or less. The precipitated oxygen does not have the ability to donate electrons like the OTDs formed from the free interstitial oxygen so subsequent heat treating processes do not further reduce the resistivity of the wafer.
The use of the gettering heat treatment is capable of reducing the oxygen content in a wafer having a resistivity of a 100 xcexa9xc2x7cm or more from 10 to 25 ppma to 8 ppma or less while generating or maintaining a bulk defect density of 1xc3x97108 to 2xc3x971010 defects/cm3. This number of defects is sufficient to provide gettering to the wafer in order to trap contaminants and prevent the contaminants from moving to the surface of the wafer. The wafer described above will maintain a consistent high resistivity through subsequent low temperature heat treatments, such as device heat treatments at 350xc2x0 C. to 500xc2x0 C., while maintaining sufficient gettering effect.
The main drawback with the above described gettering heat treatment, however, is the process time required to precipitate the oxygen within the wafer. Typically, for example, the heat treatment process may require a first heating step of 800xc2x0 C. for 4 hours, a second heat treating step of 1000xc2x0 C. for 10 hours, and a third heat treatment step of 1050xc2x0 C. for 6 hours. The extended process time required to maintain the wafer at temperature until the oxygen content of the wafer is reduced from 10 to 25 ppma to 8 ppma or less lowers the overall efficiency of the wafer making process, both in terms of time and in terms of power requirements.
What is needed is a method of providing for the oxygen precipitation heat treatment of a high-resistivity wafer in which oxygen content of the wafer is reduced from 10-25 ppma to 8 ppma or less and in which the bulk defect density is 1xc3x97108 to 2xc3x971010 defects/cm3 without the time delay and industrial expense associated with a complete oxygen precipitation heat treatment prior to the device fabrication stage of wafer production.
The invention is a method of treating a high-resistivity silicon wafer containing interstitial oxygen in such a way that the oxygen is largely precipitated, which prevents the oxygen from acting as an electron donor and prevents the resistivity of the wafer from diminishing. The invented method recognizes that heat treatment often occurs during fabrication of devices upon the surface of the wafer. The method calculates the heat treatment that will occur in the device fabrication stage. The wafer is then heat treated to an intermediate oxygen precipitation value with the expectation that the heat treatment which occurs during device fabrication will provide the additional precipitation needed to reach a final desired precipitation value.
The invented method comprises a) using the CZ method to grow a silicon single crystal ingot with a resistivity of 100 xcexa9xc2x7cm or more and an initial interstitial oxygen concentration of 10 to 40 ppma, b) processing the ingot into a wafer, c) determining the total amount of heat treatment required to reduce the interstitial oxygen content of the wafer to about 8 ppma or less, d) determining the amount of heat treatment which will take place during the device fabrication process after wafer fabrication, e) subjecting the wafer to a partial oxygen precipitation heat treatment equivalent to the total amount of heat treatment, less the amount of heat treatment that will occur during device fabrication.
The first step of the precipitation heat treatment preferably occurs in the temperature range of about 600xc2x0 C. to about 800xc2x0 C. This temperature range is optimum for creation of nucleation sites for oxygen precipitation. The nucleation sites provide for precipitation both during the wafer production and device fabrication stages.
Rather than providing the heat treatment needed to precipitate the desired amount of oxygen, the invented method anticipates heat treatments that will occur in subsequent processing steps and only provides heat treatments to precipitate the oxygen to an intermediate value. Later processes, such as device fabrication, provide the thermal energy required to precipitate the oxygen to a final value. Thus, energy and time are conserved during the wafer fabrication process.